VLSI Design

Teacher

Dr. Chandra Sekhar Dash

Category

Core Courses

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Course Name : VLSI Design

Code(Credit) : CUTM1040(3-2-1)

Course Objectives

The objective of the course is to

Provide understanding of the entire logic design process with the analysis from combinational and sequential digital circuit design.

Provide understanding of the techniques essential to the Verilog programming for Verification and Testing.

Learn the architecture of most prominent vendor in the FPGA market, Xilinx FPGAs and Altera FPGAs.

Course Outcome

COs Course outcomes Mapping COs with POs (High/Medium/Low)
CO1 Knowledge on Analytical combinational and sequential circuit design concepts PO1: Knowledge (High), PO2: Problem analysis (Medium)
CO2 Analytical Verilog coding, compiling, simulating and executing on any VLSI design platform. PO2: Problem analysis (High), PO3: Design /development of solutions (High)
CO3 Development for FSMs & ASMs for the given problems. PO5: Modern tool usage (High)
CO4 Hands-on Verilog HDL for FPGA Programming. Skill development for implementing Digital Circuits on Xilinx FPGAs and Altera FPGAs using Verilog HDL. PO5: Modern tool usage (High)

Course Syllabus

Module I: Introduction to VERILOG(10 hrs)
Introduction to Verilog HDL & Hierarchical Modeling Concepts,Lexical Conventions &DataTypes,System Tasks & Compiler Directives,Modules, Ports and Module Instantiation Methods,Modeling methods,Design Verification using Test benches.
Practice
•Introduction to Xilinx EDA Tool.
•Introduction to XST Tool and ISIM Tool.
•Xilinx Tool Flow: Simulation and Synthesis.
•Module and Ports in Verilog.
•Data Types in Verilog Programing.
Module II: Boolean Algebra and Logic Minimization(8hrs)
Binary Arithmetic and 1’s and 2’s Complementation, Basic Theorems and Properties, Canonical and Standard Form, Algebraic Simplification of Digital Logic Gates,The Karnaugh Map Method, Prime and Essential Implications, Don’t Care Map Entries.
Practice
•Gate level Modelling in Verilog.
•Data flow Modelling in Verilog.
•Behavioral Modelling in Verilog.
Module III: Combinational Circuit Design(12hrs)
Arithmetic Circuits: Adder/Subtractor Circuits, Ripple Carry Adder, Universal Ripple carry Adder, BCD Adder, MultipliersComparators, Multiplexer, Demultiplexer, Decoder, Encoder and Priority Encoder, Code Converters: Binary to Gray, Binary to BCD.
Practice
•Design of Arithmetic Circuits using Verilog.
•Design of Encoder and Decoder using Verilog.
•Design of Data selector and Data Distributor using Verilog.
•Design of comparator and Code converters using Verilog.
Module IV: Sequential Circuit Design (14hrs)
Latch, Flip-Flop: S-R,D,J-K,T, Flip-Flop Conversion and Excitations Counter: Asynchronous and Synchronous counter Design, Register: SISO, SIPO,PISO and PIPO, Universal Shift Register, Johnson Counter and Ring Counter.
Practice
•Design SR and D-Flip Flop Using Continuous and Procedural Assignments.
•Design JK-Flip Flop And T-Flip Flop Using Verilog.
•Design Shift Registers (SISO, SIPO, PISO, PIPO) using Verilog.
•Design Ripple Counter and Up/Down Synchronous Binary Counter Using Verilog.
Module V: State Machines(10 hrs)
Basic Finite state machines (FSM) structures, Mealy and Moore type FSM,Design of controller and Data path units,Controller Design using FSMs & ASMs
Practice
•Design of Sequence Detectors allowing overlapping as well as non-overlapping.
•Design of Mealy and Moore type FSM using Verilog.
•Design of data controller using ASM.
Module VI: FPGA Architecture and Prototyping (7 hrs)
Introduction to Programmable Logic and FPGAs, Popular CPLD & FPGA Families, Architecture of Xilinx and Altera FPGAs.
Practice
•Proto-typing of a design using FPGA Design Kit.
Module VII: Synthesis and Timing(6hrs)
FPGA Design Flow,Implementation Details Advanced FPGA Design tips, Logic Synthesis for FPGA, Static Timing Analysis.
Practice
•Design Mapping and Optimization.
•Analyze and Resolve Design Problems.
•Report Generation.
•Verilog Gate-Level Netlist Generation and Post-Synthesis Timing Data (SDF) Extraction.
•Design Constraints Generation for Placement and Routing.
Text Books:
1.Mano, M. M. (2005). Digital Design International Edition.
2. Palnitkar, S. (2003). Verilog HDL: a guide to digital design and synthesis (Vol. 1). Prentice Hall Professional.
Reference Books:
1. Kohavi, Z., & Jha, N. K. (2009). Switching and finite automata theory. Cambridge University Press.
2. Jain, R. P. (2003). Modern digital electronics. Tata McGraw-Hill Education.

Session 1

Introduction to Verilog HDL & Hierarchical Modeling Concepts

Video Link1: https://www.youtube.com/watch?v=q1QwC3YlHG0

Video Link2: https://www.youtube.com/watch?v=vmraRVxKYss

Lecture Note: Session 1

Session 2

Lexical Conventions, DataTypes, System Tasks & Compiler Directives

Video Link1: https://www.youtube.com/watch?v=7knDt4QB1tk

Video Link2:https://www.youtube.com/watch?v=mC1DzAuOTwM

Lecture Note: Session 2

Session 3

Modules, Ports and Module Instantiation Methods, Modeling Methods

Video Link: https://www.youtube.com/watch?v=PJGvZSlsLKs

Lecture Note: Session 3

Session 4

Practice:
• Introduction to Xilinx EDA Tool.

• Introduction to XST Tool and ISIM Tool

Tools: Xilinx ISE & CADENCE EDA Tool

Virtual Lab: https://www.multisim.com/

Session 5

Modeling methods, Design Verification using Test Benches

Video Link: https://www.youtube.com/watch?v=GcuxYosI6-M

Lecture Note: Session 5

Session 6

Binary Arithmetic

Video Link: https://www.youtube.com/watch?v=hJghJOnou88

Lecture Note: Session 6

Session 7

Binary Arithmetic (Complement Method)

Video Link: https://www.youtube.com/watch?v=Z3mswCN2FJs

Lecture Note: Session 7

Session 8

Practice

• Xilinx Tool Flow: Simulation and Synthesis

• Module and Ports in Verilog

• Data Types in Verilog Programing.

Tools : Xilinx ISE & CADENCE EDA Tool

Virtual Lab: https://www.multisim.com/

Session 9

Basic Theorom and Logic Gates

Video Link:1 https://www.youtube.com/watch?v=gI-qXk7XojA

Video Link2: https://www.youtube.com/watch?v=z9s8A8oBe7g

Lecture Note: Session 9

Session 10

Canonical Forms and Conversions

Video Link:1 https://www.youtube.com/watch?v=TMxMPJeJ_18

Video Link:2 https://www.youtube.com/watch?v=xZOQRR_SYHs

Lecture Note: Session 10

Session 12

Practice

• Gate level Modelling in Verilog

• Data flow Modelling in Verilog

Tools: Xilinx ISE & CADENCE EDA Tool

Virtual Lab: https://www.multisim.com/

Session 13

Don't Care Conditions

Video Link: https://www.youtube.com/watch?v=lPT9Ltjij1s

Lecture Note: Session 13

Session 14

Arithmetic Circuits: Adder/Subtractor Circuits

Video Link:1 https://www.youtube.com/watch?v=thkTzdnkL5U

Video Link:2 https://www.youtube.com/watch?v=m0C3-JWWvcc

Lecture Note: Session 14_1

Lecture Note: Session 14_2

Session 15

Ripple Carry Adder and Carry Look Ahead Generator

Video Link:1 https://www.youtube.com/watch?v=TXZBqtfAOpY

Video Link:2 https://www.youtube.com/watch?v=6Z1WikEWxH0

Lecture Note: Session 15

Session 16

Practice

• Behavioral Modelling in Verilog

Tools: Xilinx ISE & CADENCE EDA Tool

Virtual Lab: https://www.multisim.com/

Session 17

BCD Adder

Video Link: https://www.youtube.com/watch?v=9O7OJi7RCLQ

Lecture Note: Session 17

Session 18

Multipliers, Magnitude Comparator

Video Link:1 https://www.youtube.com/watch?v=7Bz9IgFNhDo

Video Link:2 https://www.youtube.com/watch?v=BhUUmbz76P0

Lecture Note: Session 18

Session 19

Multiplexer and Function Implementation

Video Link:1 https://www.youtube.com/watch?v=FKvnmxte98A

Video Link:2 https://www.youtube.com/watch?v=vOFeSu6Zr94

Lecture Note: Session 19

Session 20

Practice

• Design of Arithmetic Circuits using Verilog

• Design of Encoder and Decoder using Verilog

Tools: Xilinx ISE & CADENCE EDA Tool

Virtual Lab: https://www.multisim.com/

Session 21

Demultiplexer, Decoder and Function Implementation

Video Link:1 https://www.youtube.com/watch?v=-9s3xBlcBVM

Video Link:2 https://www.youtube.com/watch?v=u863cwgdlnA

Lecture Note: Session 21

Session 22

Encoder and Priority Encoder

Video Link:1 https://www.youtube.com/watch?v=I_-3HN1ueNk

Video Link:2 https://www.youtube.com/watch?v=kEj-m3YuGa4

Lecture Note: Session 22

Session 23

Code Converters: Binary to Gray, Binary to BCD

Video Link: https://www.youtube.com/watch?v=cbmh1DPPQyI

Lecture Note: Session 23

Session 24

Practice

• Design of Data selector and Data Distributor using Verilog

• Design of comparator and Code converters using Verilog

Tools: Xilinx ISE & CADENCE EDA Tool

Virtual Lab: https://www.multisim.com/

Session 26

Flip-Flop: J-K,T and Characteristic Equations

Video Link:1 https://www.youtube.com/watch?v=uiKKRPZbuXA

Video Link:2 https://www.youtube.com/watch?v=lnQD2_M9uDI

Lecture Note: Session 26

Session 27

Flip-Flop Conversion and Excitations

Video Link:1 https://www.youtube.com/watch?v=ApJ972OYyXQ

Video Link:2 https://www.youtube.com/watch?v=NytpDrESCV8

Lecture Note: Session 27

Session 28

Practice

• Design SR and D-Flip Flop Using Continuous and Procedural Assignments

• Design JK-Flip Flop And T-Flip Flop Using Verilog

Tools: Xilinx ISE & CADENCE EDA Tool

Virtual Lab: https://www.multisim.com/

Session 29

Asynchronous Counter

Video Link: https://www.youtube.com/watch?v=9O7OJi7RCLQ

Lecture Note: Session 29

Session 31

Synchronous Counter

Video Link: https://www.youtube.com/watch?v=6e8oV2blkGs

Lecture Note: Session 31

Session 32

Practice

• Design Ripple Counters Using Verilog

• Design Synchronous Counter and Up/Down Synchronous Binary Counter Using Verilog

Tools : Xilinx ISE & CADENCE EDA Tool

Virtual Lab: https://www.multisim.com/

Session 33

Synchronous Counter Design

Video Link: https://www.youtube.com/watch?v=svFUEJkoeVY

Lecture Note: Session 33

Session 36

Practice

• Design of Sequence Detectors allowing overlapping as well as non-overlapping

• Design of Mealy and Moore type FSM using Verilog

Tools : Xilinx ISE & CADENCE EDA Tool

Virtual Lab: https://www.multisim.com/

Session 38

Basic Finite State Machines (FSM) Structures

Video Link: https://www.youtube.com/watch?v=4rNYAvsSkwk

Lecture Note: Session 38

Session 39

Mealy and Moore Type FSM

Video Link:1 https://www.youtube.com/watch?v=0_OZKWdCixw

Video Link:2 https://www.youtube.com/watch?v=vdZKehWMJSM

Lecture Note: Session 39

Session 40

Practice

• Design Mapping and Optimization

• Analyze and Resolve Design Problems

• Design of data controller using ASM

Tools : Xilinx ISE & CADENCE EDA Tool

Session 41

Design of controller and Data path units

Video Link https://www.youtube.com/watch?v=1E5_8sGx3_c

Lecture Note: Session41

Session 42

Design of controller and Data path units

https://www.youtube.com/watch?v=38md9YNPee0

Lecture Note: Session42

Session 43

Controller Design using FSMs & ASMs

Video Link: .https://www.youtube.com/watch?v=jyUYvNFgnrI

Lecture Note: Session43

Session 44

Project

Session 45

Controller Design using FSMs & ASMs

Video Link: https://www.youtube.com/watch?v=ntiv1g7G_C4

Lecture Note: Session45

Session 46

Introduction to Programmable Logic and FPGAs

Video Link:1 https://www.youtube.com/watch?v=H27ARuZdeNQ

Video Link:2 https://www.youtube.com/watch?v=qPgm36V4OXs

Lecture Note: Session 46

Session 47

CPLD & FPGA Families

Video Link: https://www.youtube.com/watch?v=KUWbqaOuzOw

Lecture Note Session 47

Session 48

Project

• Prototyping of a design using FPGA Design Kit

Tools: Xilinx ISE Design Suite and Spartan FPGA Kit

Virtual Lab: https://www.multisim.com/

Session 49

Architecture of Xilinx PFPGAs

Video Link: https://www.youtube.com/watch?v=0nMHJ0VoYhY

Lecture Note: Session 49

Session 50

Architecture of ARTERA FPGAs

https://www.youtube.com/watch?v=krPCFK4TJ5s

Lecture Note: Session 50

Session 51

Architecture of ALTERA FPGAs

Video Link: https://www.youtube.com/watch?v=z2ivjyBiTG8

Lecture Note: Session 51

Session 52

Project

• Verilog Gate-Level Netlist Generation and Post-Synthesis Timing Data (SDF) Extraction

• Design Constraints Generation for Placement and Routing

Tools: Xilinx ISE Design Suite and Spartan FPGA Kit

Session 53

Logic Synthesis for FPGA

Video Link:1 https://www.youtube.com/watch?v=TSx2svUv71c

Video Link:2 https://www.youtube.com/watch?v=SSxAuMY5wFo

Lecture Note: Session 53

Session 54

Static Timing Analysis

Video Link:1 https://www.youtube.com/watch?v=M36sBRU8LpI

Video Link:2 https://www.youtube.com/watch?v=Hxq1Xmr4Rpw

Lecture Note: Session 54

Projects


•Design of Edge Detector using Verilog and Implementation in FPGA.

•Design and Implementation of 64 Bit ALU using Verilog.

•Design and Implementation of SRAM using Verilog.

•Design of 32 Bit Carry Look Ahead Adder Using Verilog in FPGA.

•Design and Implementation of Real Time Traffic Light Control System Using FPGA.

Our Main Teachers

Dr. Chandra Sekhar Dash

Assistant Professor, Department of ECE , SoET
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Dr. Chandra Sekhar Dash currently works as Assistant Professor in the Department of Electronics and Communication Engineering at Centurion University of Technology and Management, Odisha. His research interests include Semiconductor Non-Volatile Memory (NVM) Technology and its Advanced Applications, Electronics Materials and VLSI Circuits. Dr. Chandra Sekhar Dash received his Ph.D and Masters from VIT University, […]

Satyanarayan Padhy

Assistant Professor, Department of ECE , SoET
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Satyanarayan Padhy currently working as Assistant Professor in the Department of Electronics and Communication Engineering at Centurion University of Technology and Management, Odisha. His research interests include Digital System Design,Signal Processing and Controller design for power converters. He has received his M.Tech from NIT, Allahabad, India in the Year 2013 and Currently Pursuing his PhD. […]

Sandipan Pine

Associate Professor, Dept of ECE, SOET, Paralakhemundi
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Sandipan Pine currently working as Associate Professor in the Department of Electronics and Communication Engineering at Centurion University of Technology and Management, Odisha. His research interests include Chip design and robotics area.He has received his M.Tech from IIT kharagpur in Microelectronics and VLSI and Currently Pursuing his PhD from Utkal University. He has published more […]